{"id":187,"date":"2022-12-18T08:12:16","date_gmt":"2022-12-18T16:12:16","guid":{"rendered":"http:\/\/www.qsigmainc.com\/?page_id=187"},"modified":"2025-03-27T16:23:04","modified_gmt":"2025-03-27T21:23:04","slug":"events","status":"publish","type":"page","link":"https:\/\/www.qsigmainc.com\/?page_id=187","title":{"rendered":"Papers"},"content":{"rendered":"\n

Published Papers by Earle Jennings<\/h2>\n\n\n\n

2017<\/strong><\/h3>\n\n\n\n

IEEE International Conference on Rebooting Computing at Washington, D.C. November 8-9, 2017<\/strong>
\nInvited Poster with Publication Presentation by Earle Jennings:
\n   “Securing Data Centers, Handling Computers, and Networked Sensors Against Viruses and Rootkits”
\n<\/strong>    Published in: 2017 IEEE International Conference on Rebooting Computing (ICRC)<\/span><\/a> <\/em><\/span>
\n<\/strong>   Abstract:<\/strong>
\n<\/strong>Today’s data centers, their handheld computers and network sensors, are discussed in terms of how they are penetrated by viruses and rootkits. This paper then presents a new computer architecture, implemented to be semantically compatible with an existing microprocessor, along with modification of several system components commonly found in data centers. The new computer architecture physically separates instruction memories from data-related memories removing the possibility of installing viruses and rootkits. Application compatibility is insured by the semantic compatibility of the cores with the existing superscalar microprocessor. Communications, memory controllers, and memory devices throughout the data center, handheld computers and network sensors physically segregate task-instruction information from data-related information to further remove any opportunity for these hidden threats becoming installed threats.<\/span><\/h3>\n\n\n\n

Tenth Workshop on Fault-Tolerant Spaceborne Computing Employing New Technologies, 2017 at Sandia National Lab, Albuquerque, NM May 29-June 2, 2017
\n<\/strong>Presentation by Earle Jennings:
\n“New Computer Architecture to Resist Viruses and Rootkits”<\/strong><\/p>\n\n\n\n

Super Computing Frontiers and Innovations Journal – 2017<\/strong>
\nTwo papers by Earle Jennings:
\n   <\/b>“Simultaneous Transmit <\/b>and<\/b><\/span> Receive (STAR) Messaging Protocol”<\/b><\/a>
\nand
\n   \u201cCore Module Optimizing PDE Sparse Matrix Models With HPCG Example\u201d<\/a><\/strong>
\n<\/strong><\/p>\n\n\n\n

India Institute of Science, hosted by Prof. S.Khttp:\/\/superfri.org\/index.php\/superfri\/article\/view\/135. Nandy, March 22<\/strong>
\nEarle Jennings talk:
\n   “Cores for Embedded Controllers and Super Computers- synergistic research results”<\/strong><\/p>\n\n\n\n

Super Computing Frontiers Conference, March 13 – 16, 2017,\u00a0<\/strong>Singapore

<\/strong>Earle Jennings presentations:

\u00a0 \u00a0\u201cCompile-Time Reconfigurable Superscalar Computer Architecture\u201d<\/a>, <\/strong>and

\u00a0\u00a0 “Simultaneous Transmit And Receive (STAR) Messaging Protocol”<\/a><\/strong><\/p>\n\n\n\n

2016<\/strong><\/h3>\n\n\n\n

ICCEE 2016,\u00a0The 9th<\/sup> International Conference on Computer and Electrical Engineering,\u00a0Dec 7\u00a0–\u00a011,\u00a0<\/strong>Barcelona, Spain

<\/strong>Earle Jennings presentation:

\u201cSimultaneous Multi-Processor Cores for Efficient Embedded Applications\u201d.

<\/strong>Paper published in Journal of Computers<\/u><\/a>.<\/p>\n\n\n\n

SC 16, The Emerging Technologies Showcase,  Nov 15 – 17, <\/strong>Salt Lake City, Utah
\n<\/sup>Earle Jennings presentation:
\n   Reconfigurable Compile-time Superscalar Computer<\/a><\/strong><\/p>\n\n\n\n

ARM Research Summit, Sept 15 – 16, Churchill College<\/strong>, Cambridge, England
\nEarle Jennings presentation:
\n\u201cSimultaneous Multi-Processor Cores for Efficient Embedded Applications<\/strong>\u201d
\nPoster presentation:
\n\u201cTransforming Today\u2019s Superscalar Instruction  Interpreter into a Compile-time Utility\u201d<\/strong><\/p>\n\n\n\n

Unpublished Papers by Earle Jennings<\/h2>\n\n\n\n

2022<\/strong><\/h3>\n\n\n\n

\u00a0“SiMulPro Core Emulations Show Near Linear Performance Scale-up with Inner Loop Optimization of an O(N^2) Function”<\/strong><\/a><\/h3>\n\n\n\n

2016<\/strong><\/p>\n\n\n\n

“Application Configurable DRAM Memory Management for HPC and Big Data”<\/strong><\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

Published Papers by Earle Jennings 2017 IEEE International Conference on Rebooting Computing at Washington, D.C. November 8-9, 2017 Invited Poster with Publication Presentation by Earle Jennings:    “Securing Data Centers, Handling Computers, and Networked Sensors Against Viruses and Rootkits”   … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":75,"parent":0,"menu_order":2,"comment_status":"closed","ping_status":"closed","template":"onecolumn-page.php","meta":{"footnotes":""},"class_list":["post-187","page","type-page","status-publish","has-post-thumbnail","hentry"],"_links":{"self":[{"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=\/wp\/v2\/pages\/187","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=187"}],"version-history":[{"count":60,"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=\/wp\/v2\/pages\/187\/revisions"}],"predecessor-version":[{"id":404,"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=\/wp\/v2\/pages\/187\/revisions\/404"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=\/wp\/v2\/media\/75"}],"wp:attachment":[{"href":"https:\/\/www.qsigmainc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=187"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}